1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to forming capacitors in the metallization system, such as capacitors for dynamic random access memories (DRAMs), decoupling capacitors and the like.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS and PMOS elements, resistors, capacitors and the like are formed on a single chip area. Typically, feature sizes of these circuit elements are steadily decreasing with the introduction of every new circuit generation to provide currently available integrated circuits with an improved degree of performance in terms of speed and/or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size commonly brings about an increased switching speed, thereby enhancing signal processing performance while, however, increasing dynamic power consumption of the individual transistors. That is, due to the reduced switching time period, the transient currents, upon switching a CMOS transistor element from logic low to logic high, are significantly increased.
In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors, are typically formed in integrated circuits that are used for a plurality of purposes, such as for decoupling. Decoupling in integrated circuits is an important aspect for reducing the switching noise of the fast switching transistors, since the decoupling capacitor may provide energy at a specific point of the circuitry, for instance, at the vicinity of a fast switching transistor, and thus reduce voltage variations which may otherwise unduly affect the logic state represented by the transistor.
Due to the decreased dimensions of circuit elements, not only the performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC). Furthermore, in sophisticated microcontroller devices, an increasing amount of storage capacity may be provided on chip with the CPU core, thereby also significantly enhancing the overall performance of modern computer devices. For example, in typical microcontroller designs, different types of storage devices may be incorporated to provide an acceptable compromise between die area consumption and information storage density versus operating speed. For instance, fast or temporary memories, so-called cache memories, may be provided in the vicinity of the CPU core, wherein respective cache memories may be designed to allow reduced access times compared to external storage devices. Since a reduced access time for a cache memory may typically be associated with a reduced storage density thereof, the cache memories may be arranged according to a specified memory hierarchy, wherein a level 1 cache memory may represent the memory formed in accordance with the fastest available memory technology. For example, static RAM memories may be formed on the basis of registers, thereby enabling an access time determined by the switching speed of the corresponding transistors in the registers. Typically, a plurality of transistors may be required to implement a corresponding static RAM cell. In currently practiced approaches, up to six transistors may typically be used for a single RAM memory cell, thereby significantly reducing the information storage density compared to, for instance, dynamic RAM memories including a storage capacitor in combination with a pass transistor. Thus, a higher information storage density may be achieved with DRAMs, although at an increased access time compared to static RAMs, which may render dynamic RAMs attractive for specific, less time-critical applications in complex semiconductor devices. For example, typical cache memories of level 3 may be implemented in the form of dynamic RAM memories so as to enhance information density within the CPU, while only moderately sacrificing overall performance.
Frequently, the storage capacitors may be formed in the transistor level using a vertical or planar configuration. While the planar architecture may require significant silicon area for obtaining the required capacitance values, the vertical arrangement may necessitate complex patterning regimes for forming the trenches of the capacitors. Consequently, the respective trenches for accommodating an appropriate capacitor dielectric and capacitor electrode materials may have to extend deeply into the semiconductor material to provide the desired high capacitance. For example, for advanced semiconductor devices including an embedded DRAM area, a depth of up to 8 μm may be required with respect to achieving the required capacitance. The etch process for forming deep trenches therefore represents highly critical process steps during the formation of embedded DRAM areas, since the precise depth, the sidewall angles and the like may essentially influence the finally obtained performance of the respective capacitors.
Consequently, sophisticated etch processes on the basis of appropriate plasma ambients have been established for silicon-based transistors with a bulk configuration, in which the active region of the transistor is electrically connected to the substrate material. During a corresponding anisotropic etch process, an appropriate plasma atmosphere is generated in which reactive ions are created and are accelerated towards the surface to be etched in order to obtain a high directionality for providing a moderately high physical component, which is substantially oriented perpendicular to the surface of interest. Furthermore, respective polymer materials may be added to the etch ambient of the respective anisotropic etch process in order to appropriately reduce a lateral etch component, while substantially not affecting the vertical progress of the corresponding etch front. Due to the highly complex conditions within the plasma etch ambient, which may even alter with the height level within the opening, highly stable process conditions are required to achieve a uniform process result. In particular, since a high degree of directionality has to be maintained within the etch opening during the ongoing etch process, the bias voltage applied between the plasma ambient and the substrate represents a critical process parameter, which may significantly affect the etch rate and also the degree of directionality, in particular if deep trenches up to 8 μm may have to be etched. Typically, the respective bias voltage may be established on the basis of a DC voltage source or on the basis of RF (radio frequency) bias generators, which may be controlled with high accuracy. However, the actually effective bias voltage at the substrate is substantially determined by the local conditions of the substrate to be etched, wherein, in particular, conductive areas of extended size may significantly reduce the effect of the external bias voltage sources when the corresponding areas may not be tied to a defined potential. This may be accomplished in a bulk configuration by connecting the substrate with the external bias voltage source, thereby also creating the same potential in the respective regions of the substrate material in which the deep trench is to be formed.
In SOI architectures, which are frequently used in sophisticated semiconductor devices, the active semiconductor layer is electrically insulated from the substrate portion, thereby resulting in significantly different etch conditions, which may result in even more complex process conditions. Hence, a high capacitance value in the transistor level may require large area and/or very complex manufacturing techniques.
For these reasons, in some approaches, capacitors may be formed in the metallization level of semiconductor devices, thereby avoiding the complex process sequence in the transistor level described above. However, in advanced semiconductor devices formed on the basis of highly conductive metals, such as copper, possibly in combination with low-k dielectric materials, the additional processes and materials used for the capacitor may also affect other components in the metallization level, thereby possibly also compromising performance of the metallization level system.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.